Memory hierarchy and cache

Principles

smaller is faster. (in cache view point)
a program property is locality.

1. Temporal locality : referenced data tend to be referenced again soon. (e.g. loops)
2. Spatial locality : if some data are referenced, data beside the referenced data tend to be referenced soon.

Hit Time << Miss Penalty so can Memory Hierarchy exist.

Registers - L1 Cache - L2 Cache - L3 Cache - DRAM - Disk

Registers are managed in code generation, which is by compiler.
Caches are managed by hardware.
DRAM and Disk are managed by OS.

Why Virtual Memory is fully associative?

Disk is too slow. Calculation and then placing a page in a good place doesn't take too much time. The penalty to replace them between Disk and DRAM is much higher than calculation.

Block placement : fully associative, direct mapped(1-way associative), set-associative
Write strategy : Write through, Write back

Write through will write to lower layer simultaneously when writing in upper layer, e.g. when write to cache, it write to main memory simultaneously. It need write buffer to queue the writes to memory.

 Write back means you can write many times in upper layer and it become dirty state, but it don't write to memory until this block become victim block and need to be replace.

Write around, ............